By P. Quinn, et al.

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Additional info for High-Accuracy Switched-Capacitor Techniques - Applied to Filter and ADC Design

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9) Note a better formulation for τ , for the sake of more insightful calculations, is: τ= 1 gm È C L(total ) ˘ ◊Í β + Cin(total ) ˙ . 10) Hence, for the circuit of Fig. 3(c), the linear time constant becomes: τ= 1 gm )( È ◊ Í C L + Cout par ◊ ÍÎ ( Cin +Cin par +C fb C fb )+ C ( in ˘ + Cin par ˙ . 2% between clock transitions. A DC gain of 65-70dB is achievable down to low supply voltages without compromising the settling response. 1% error tolerance for incomplete settling ( εd ). For a single-sampling realization, a maximum of half a clock period is allowed for settling, requiring τ < T 14.

20) For the usual operating conditions of analogue circuits, it has been shown that VT mismatch dominates over β mismatch [37]. The condition for which both sources of mismatch make an equal contribution to the random input offset voltage is defined by the corner Von voltage, VonC : VonC = 2 ◊ AVT Aβ . 0V. 20) dominate the β mismatch terms. Von p is often two to three times larger than Vonn for the following main reasons. Since the PMOST current sources don’t need to have a large gm, β p of the PMOST current sources is usually a lot less than βn of the input stage.

Under equilibrium conditions, the drain-source voltage of each input stage MOST is set at: ( ) Vds(input pair ) = Von + Vm arg in . 3 Influence of Channel Mobility Factor The value for the mobility factor, µ, used in the preceding formulae for the MOST β factor, is not constant. 3. Design Procedure for Optimized Settling 29 when determining the Von, where the simplified single-dimensional MOST model is no longer totally accurate [38]. The first effect of interest is vertical field mobility degradation, where the field between the gate and the channel causes the charge carriers in the channel to slow down for high gate-source voltages due to the increasing pull on the inversion layer towards the gateoxide silicon interface.

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High-Accuracy Switched-Capacitor Techniques - Applied to Filter and ADC Design by P. Quinn, et al.


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