By Gert Jervan.
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Additional resources for High-level test generation and built-in self-test techniques for digital systems
75 923 4,475 Table 1. Results for the DIFFEQ benchmark circuit. 55 We have also investigated possibilities to apply our ATPG approach to an industrial design F4 , which is part of the F4/F5 layer of the ATM protocol, covering the main functionality as specified by standard references. The F4/F5 layer covers the Operation and Maintenance (OAM) functionality of the ATM switches. The F4 level handles the OAM functionality concerning virtual paths and the F5 level handles the OAM functionality concerning virtual channels.
Solving such a test case successfully means that the generated low-level test vector can be justified till the primary inputs and the fault effect is observable at the primary outputs. If the constraint solver cannot find an input combination that would satisfy the given constraints, another combination of values for the undefined bits has to be chosen and the constraint solver should be employed again. This process is continued until a solution is found or a timeout occurs. If there is no input combination that satisfies the generated test case, the given low-level test pattern will be abandoned and the gate level ATPG will be employed again to generate a new low-level test pattern.
We have extracted two blocks from the specification: F4_InputHandler_1 and F4_OutputHandler_1. 30% Table 2: ATPG results with F4 design As it can be seen, HTG can produce results which are comparable with results obtained at the gate level, while having shorter test generation time and reduced test length. In case of the F4_InputHandler_1 block, our HTG approach obtains even higher fault coverage figure than that of the gate-level ATPG. This illustrates very well the situation when a gate-level ATPG cannot produce high quality test vectors due to the higher complexity of descriptions at lower levels of abstraction, and a high-level ATPG tool can outperform a gate-level ATPG tool by producing test patterns with higher fault coverage.
High-level test generation and built-in self-test techniques for digital systems by Gert Jervan.