By P. R. van der Meer, A. van Staveren, A. H. M. van Roermund (auth.)

ISBN-10: 1402028490

ISBN-13: 9781402028496

ISBN-10: 1475710577

ISBN-13: 9781475710571

1. 1 Power-dissipation tendencies in CMOS circuits Shrinking machine geometry, growing to be chip quarter and elevated data-processing pace functionality are technological tendencies within the built-in circuit to magnify chip performance. Already in 1965 Gordon Moore envisioned that the whole variety of units on a chip may double each year until eventually the Nineteen Seventies and each 24 months within the Eighties. This prediction is well known as "Moore's legislations" and finally culminated within the Semiconductor organization (SIA) expertise street map [1]. The SIA highway map has been a consultant for the in­ dustry best them to endured wafer and die dimension progress, elevated transistor density and working frequencies, and illness density aid. to say a number of numbers; the die measurement elevated 7% in keeping with 12 months, the smallest characteristic sizes lowered 30% and the working frequencies doubled each years. as a result of those developments either the variety of transistors and the ability dissi­ pation in keeping with unit quarter raise. within the close to destiny the utmost strength dissipation consistent with unit zone could be reached. Down-scaling of the provision voltage is not just the simplest technique to decrease energy dissipation generally it is also an important precondition to make sure machine reliability through decreasing electric fields and machine temperature, to avoid gadget degradation. A draw-back of this answer is an elevated sign propa­ gation hold up, which leads to a reduce data-processing velocity performance.

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Extra info for Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction

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X 10 - 7 1. X I,' -- ----- - - - - -- -f- f--- ~~ It' I,' 10 - 9 I 1. 1. X X 10 - 11 10 - 13 /" ... , ...... / I / ... ,,. 17. 5 V (upper curve), showing DIBL. 1 V and with the drain-source voltage and the weak-inversion slope increases, reflecting the increase in drain leakage [32]. Channel edge current. Technological developments to boost integration densities not only focus on shrinking device geometries, but also on reducing transistor isolation areas. 35ILm. 251Lm CMOS technology. e. tetraethylorthosilicate (TEOS) is deposited in a trench, allowing for a completely abrupt transition.

001 " / 0 . 00001 1. X 10 - 7 1. X I,' -- ----- - - - - -- -f- f--- ~~ It' I,' 10 - 9 I 1. 1. X X 10 - 11 10 - 13 /" ... , ...... / I / ... ,,. 17. 5 V (upper curve), showing DIBL. 1 V and with the drain-source voltage and the weak-inversion slope increases, reflecting the increase in drain leakage [32]. Channel edge current. Technological developments to boost integration densities not only focus on shrinking device geometries, but also on reducing transistor isolation areas. 35ILm. 251Lm CMOS technology.

Ugs 0 0. 2 0. 8 [V] 1 The weak-inversion hump revealing edge leakage currents. Reverse bias leakage. Source-bulk and drain-bulk pn-junctions are reverse biased during normal operation of an MOS transistor. The resulting reverse-bias leakage current can be divided into two parts: • reverse saturation current; • generation current. The reverse saturation current is the fundamental reverse-bias current in a pn-junction. The generation current is the pn-junction current produced by the thermal generation of electron-hole pairs within the space charge region.

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Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction by P. R. van der Meer, A. van Staveren, A. H. M. van Roermund (auth.)


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